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DTSTAMP:20260630T225152Z
UID:c75dddca-6aff-4150-b852-415fc4830e38
DTSTART:20160504T060000Z
DTEND:20160505T160000Z
DESCRIPTION:Hardware technologies in High Performance Computing are continu
 ously undergoing major changes and rapidly increasing performance capabili
 ties\, but the software and the underlying code legacy is often left uncha
 nged or even neglected. This leads to performance gaps and underutilized h
 ardware assets. In this workshop you will learn from experts how to tackle
  these issues and make sure your code is ready to perform on tomorrow’s 
 HPC processing technologies.\n\nThe aims of this course are:\n\n1) To prov
 ide the attendants with an overview of the current and next Intel Xeon and
  Xeon Phi architectures and2) To teach the tools in order to get from thos
 e architectures  the maximum in terms of performance.\n\nTarget Audience\
 n\nHPC users and developers\n\nTopics\n\nCompilers\, profilers\, tools and
  techniques for optimization.\n\nPrerequisites\n\nC/Fortran\, MPI\, OpenMP
 \n\nGrant\nThe lunch for the two days will be offered to all the participa
 nts and some grants are available. The only requirement to be eligible is 
 to be not funded by your institution to attend the course and to work or l
 ive in an institute outside the Bologna area. The grant  will be 200 euro
 s for students working and living outside Italy and 100 euros for students
  working and living in Italy. Some documentation will be required and the 
 grant will be paid only after a certified presence of minimum 80% of the l
 ectures.\n\nFurther information about how to request the grant\, will be p
 rovided at the confirmation of the course: about 3 weeks before the starti
 ng date.\n\n \n\n \n\nhttps://events.prace-ri.eu/event/496/
SUMMARY:Enabling Software for High Scalable INTEL Architecture @ CINECA
URL;VALUE=URI:https://events.prace-ri.eu/event/496/
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