BEGIN:VCALENDAR VERSION:2.0 PRODID:icalendar-ruby CALSCALE:GREGORIAN BEGIN:VEVENT DTSTAMP:20260708T072426Z UID:cbc98cb7-fe52-4640-ba3e-e4b213ff35a5 DTSTART:20200129T080000Z DTEND:20200130T150000Z DESCRIPTION:Annotation\n\nWith the petering-out of Moore's law and the end of Dennard's scaling\, the pace dictated on the performance increase of Hi gh Performance Computing Systems among generations has led to power constr ained architectures and systems. In addition power consumption represents a significant cost factor in the overall HPC system economy. For those rea sons in recent years\, researchers\, supercomputing centres and major vend ors have developed new tools and methodologies to measure and optimise the energy consumption of large scale high performance system installation. D ue to the link between energy consumption\, power consumption\, and execut ion time of the application executed by the final user\, it is important f or tools and methodology to consider all of these aspects\, empowering the final user and the system administrator with the capability of finding th e best configuration given different high level objectives.\n\nThe school will give an introductory course on the fundamental concept of power consu mption and energy efficiency in HPC systems. Then it will focus on the mec hanisms that today's computing elements and systems provide in terms of mo nitoring and control of power and energy dissipation. As well as insights on the European Processor Initiative power management design. Finally it w ill introduce and give a hands-on for a set of tools for reducing the ener gy consumption in HPC devices.  \n\nThe school is organised into four mai n sessions\, driving the audience from the physical and engineering princi ples underlying power consumption in supercomputing systems to the practic al usage of state-of-the-art tools for monitoring and controlling the ener gy efficiency of supercomputing machines and workloads. The tools that wil l be covered are the MSR-SAFE (LLNL)\, MERIC (IT4I)\, COUNTDOWN (UNIBO) an d Io2s (TUD).\n\nLevel\n\nIntermediate\n\nLanguage\n\nEnglish\n\nPurpose o f the course (benefits for the attendees)\n\nBy the end of the course\, pa rticipants will be expected to:\n\n\n have a good understanding of the pri nciples underlying power consumption and energy dissipation in high perfor mance computing nodes\n recognise trade-offs and the implications of chang ing the power consumption in scientific computing systems during the execu tion of scientific computing applications\n have a clear idea of the state -of-the-art and of practices in controlling the power consumption and ener gy efficiency of supercomputing nodes and processors\n learn the internals and the usage of a set of user-space run-time libraries for controlling/o ptimising the power consumption and energy efficiency in x86 computing nod es while executing user's applications\n learn how to use these tools to o ptimise the energy consumption of your codes.\n\n\nAbout the tutors\n\nLub omir Riha is the Head of the Infrastructure Research Lab at IT4Innovation s National Supercomputing Center. Previously he was a senior researcher in the Parallel Algorithms Research Lab at IT4Innovations\, and a research s cientist in the High Performance Computing Lab at George Washington Univer sity\, ECE Department. He received his PhD and MSc degrees in Electrical E ngineering from the Czech Technical University in Prague\, the Czech Repub lic\, in 2011\, and his Ph.D. degree in Computer Science from Bowie State University\, USA. Currently he is a local principal investigator of the H2 020 Center of Excellence project POP2. Previously he was an investigator i n the FP7 EXA2CT project and the Intel Parallel Computing Center\, as well as a local principal investigator of the H2020-FET HPC READEX project. He is also co-principal developer of the ESPRESO finite element library\, wh ich includes a parallel sparse solver designed for supercomputers with ten s or hundreds of thousands of cores\, with support for both GPU and Intel Xeon Phi accelerators. His research interests are optimisation of HPC appl ications\, energy efficient computing\, acceleration of scientific and eng ineering applications using GPU and many-core accelerators\, development o f scalable linear solvers\, parallel rendering on new HPC architectures\, and signal and image processing.\n\nOndrej Vysocky received his M.Sc. deg ree in Computer Science from Brno University of Technology\, Czech Republi c in 2016. His masters thesis focused on parallel I/O optimisation. Curren tly he is a PhD student at VSB – Technical University of Ostrava\, Czech Republic\, and he simultaneously works at IT4Innovations in the Infrastr ucture Research Lab. His research is focused on energy-efficiency in high performance computing. He was also an investigator of the Horizon 2020 REA DEX project\, which deals with energy efficiency of High Performance Compu ting applications using dynamic tuning. He has since been developing a ME RIC library\, a tool for energy measurement and hardware parameter tuning during parallel application runs.\n\nAndrea Bartolini received a Ph.D. deg ree in Electrical Engineering from the University of Bologna\, Italy\, in 2011. He is currently an assistant professor in the Department of Electric al\, Electronic and Information Engineering (DEI) at the University of Bol ogna. Previously\, he was post-doctoral researcher in the Integrated Syste ms Laboratory at ETH Zurich. Since 2007 Dr Bartolini has published more th an 100 papers in peer-reviewed international journals and conferences with a focus on dynamic resource management for embedded and HPC systems. Sinc e one year Dr Bartolini leads the power management co-design of the Europe an Processor Initiative design.\n\nDaniele Cesarini graduated in Computer Engineering from the University of Bologna in 2014\, where he also earned a PhD degree in Electrical Engineering from the Department of Electrical\ , Electronic and Information Engineering in 2019. He is currently an HPC s oftware engineer at CINECA\, the Italian National Supercomputing Center\, where he works in the area of performance optimisation on large-scale scie ntific applications for the new generation of heterogeneous HPC architectu res. His research interests also concern the development of SW-HW co-desig n strategies as well as algorithms for parallel programming support for en ergy-efficient HPC systems.\n\nRobert Schöne works as a post-doc at Techn ische Universität Dresden\, where he also received his PhD. His research includes micro-architectural features of processors\, as well as tools and methods for measuring and tuning performance and energy-efficiency of par allel applications. After he received his diploma\, he worked in different projects that targeted the measurement and tuning of energy-efficiency of computer systems. Among other things\, he described and implemented inter faces that extend performance measurement frameworks for such cases. He wa s also part of the team that developed the Bull specific power and energy measurement framework HDEEM. After his PhD\, he was the scientific manager of the Horizon2020 project READEX\, which implemented an automated tool s uite for energy efficiency optimisation. Currently\, he teaches at the Fac ulty of Computer Science. Since he received his diploma\, he has published more than 30 papers\, and organised and co-organised four workshops with a focus on auto-tuning and energy-efficiency.\nhttps://events.prace-ri.eu/ event/964/ SUMMARY:Energy Efficiency in HPC @ IT4Innovations URL;VALUE=URI:https://events.prace-ri.eu/event/964/ END:VEVENT END:VCALENDAR