BEGIN:VCALENDAR
VERSION:2.0
PRODID:icalendar-ruby
CALSCALE:GREGORIAN
BEGIN:VEVENT
DTSTAMP:20260706T125508Z
UID:29b87701-7627-455c-a5bb-d347b68c6dec
DTSTART:20180621T070000Z
DTEND:20180622T160000Z
DESCRIPTION:          \n\nContents\n\nIn the ever-growing complexity 
 of computer architectures\, code optimization has become the main route to
  keep pace with hardware advancements and effectively make use of current 
 and upcoming High Performance Computing systems.\n\nHave you ever asked yo
 urself:\n\nWhere does the performance of my application lay? \n	What is th
 e maximum speed-up achievable on the architecture I am using? \n	Is my imp
 lementation matching the HPC objectives?\nIn this workshop\, we will answe
 r these questions and provide a unique opportunity to learn techniques\, m
 ethods and solutions on how to improve code\, how to enable the new hardwa
 re features and how to use the roofline model to visualize the potential b
 enefits of an optimization process. \n\nWe will begin with a description 
 of the latest micro-processor architectures and how the developers can eff
 iciently use modern HPC hardware\, in particular the vector units via SIMD
  programming and AVX-512 optimization and the memory hierarchy.\n\nThe att
 endees are then conducted along the optimization process by means of hands
 -on exercises and learn how to enable vectorization using simple pragmas a
 nd more effective techniques\, like changing data layout and alignment.\n\
 nThe work is guided by the hints from the Intel® compiler reports\, and u
 sing Intel® Advisor.\n\nWe provide also an N-body code\, to support the d
 escribed optimization solutions with practical hands-on.\n\nThe course is 
 a PRACE training event.\n\nLearning Goals\n\nThrough a sequence of simple\
 , guided examples of code modernization\, the attendees will develop aware
 ness on features of multi and many-core architecture which are crucial for
  writing modern\, portable and efficient applications.\n\nA special focus 
 will be dedicated to scalar and vector optimizations for the latest Intel
 ® Xeon® Scalable processor\, code-named Skylake\, which is going to be u
 tilized in the upcoming SuperMUC-NG machine at LRZ. The tutorial will have
  presentations and demo session.\n\nWe will provide to the attendees acces
 s to Skylake processors and Intel® tools using VM instances provided by G
 oogle Cloud Platform.\n\nThe workshop interleaves frontal and practical se
 ssions. Here the outline:\n\nDay 1\n\n09:00-09:45       Introduction
 \n\n09:45-10:30       Login to Google cloud machines\n\n10:30-11:00
        Coffee Break\n\n11:00-12:00       Code modernization ap
 proach\n\n12:00-12:30       Scalar optimization\n\n12:30-13:30   
     Lunch\n\n13:30-14:30       Compiler autovectorization\n\n14:3
 0-15:00       Data layout from AoS to SoA\n\n15:00-15:30      
  Coffee Break\n\n15:30-16:00       Memory access optimization\n\n16:
 00-16:30       SDLT (Intel SIMD Layout Templates)\n\n16:30-17:00  
      Explicit vectorization\n\n17:00-17:45       Skylake optimiz
 ation\n\n17:45-18:00       Wrap-up\n\nDay 2\n\n09:00-09:30     
   Introduction to roofline model\n\n09:30-10:30       Intel Advisor
  analysis\n\n10:30-11:00       Coffee Break\n\n11:00-12:30     
   Intel Advisor hands-on\n\n12:30-13:30       Lunch\n\n13:30-14:00
        What’s new in Intel Advisor 2019\n\n14:00-15:00      
  Introduction to MKL\n\n15:00-15:30       Coffee Break\n\n15:30-16:3
 0       Hands-on MKL\n\n16:30-17:00       What’s new in Inte
 l Parallel Studio 2019\n\n17:00-17:30       Open discussion and feed
 back\n\n17:30-18:00       Wrap-up\n\nPlease bring your own laptop (w
 ith X11 support and an ssh client installed) for the hands-on sessions! Fo
 r GUI applications we require the installation of vncviewer (https://www.r
 ealvnc.com/en/connect/download/viewer/ )”.\n\n \n\nAbout the Lecturers\
 n\nFabio Baruffa is a software technical consulting engineer in the Develo
 per Products Division (DPD) of the Software and Services Group (SSG) at In
 tel. He is working in the compiler team and provides customer support in t
 he high performance computing (HPC) area. Prior at Intel\, he has been wor
 king as HPC application specialist and developer in the largest supercompu
 ting centers in Europe\, mainly the Leibniz Supercomputing Center and the 
 Max-Plank Computing and Data Facility in Munich\, as well as Cineca in Ita
 ly. He has been involved in software development\, analysis of scientific 
 code and optimization for HPC systems. He holds a PhD in Physics from Univ
 ersity of Regensburg for his research in the area of spintronics device an
 d quantum computing.\n\nLuigi Iapichino holds a position of scientific com
 puting expert at LRZ and he is member of the Intel Parallel Computing Cent
 er (IPCC). His main tasks are code modernization for many-core systems\, a
 nd HPC support. He got in 2005 a PhD in physics from TU München\, working
  at the Max Planck Institute for Astrophysics. Before moving to LRZ in 201
 4\, he worked at the Universities of Würzburg and Heidelberg\, involved i
 n research projects related to computational astrophysics.\n\nhttps://even
 ts.prace-ri.eu/event/727/
SUMMARY:HPC code optimization workshop @ LRZ
URL;VALUE=URI:https://events.prace-ri.eu/event/727/
END:VEVENT
END:VCALENDAR