This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy and apply it to different algorithms from computational science. Architectural details that are relevant for performance, such as pipelining, SIMD, superscalarity, memory hierarchies, etc., are covered in due detail.

The course is a PRACE training event.

Introduction

    Our approach to performance engineering
    Basic architecture of multicore systems: threads, cores, caches, sockets, memory
    The important role of system topology


Tools: topology & affinity in multicore environments

    Overview
    likwid-topology and likwid-pin


Microbenchmarking for architectural exploration

    Properties of data paths in the memory hierarchy
    Bottlenecks
    OpenMP barrier overhead


Roofline model: basics

    Model assumptions and construction
    Simple examples
    Limitations of the Roofline model


Pattern-based performance engineering
Optimal use of parallel resources

    Single Instruction Multiple Data (SIMD)
    Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
    Simultaneous Multi-Threading (SMT)


Tools: hardware performance counters

    Why hardware performance counters?
    likwid-perfctr
    Validating performance models


Roofline case studies

    Dense matrix-vector multiplication
    Sparse matrix-vector multiplication
    Jacobi (stencil) smoother


Optional: The ECM performance model

https://events.prace-ri.eu/event/821/