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DTSTAMP:20260708T205730Z
UID:9b15d4f2-0cda-4ffa-8499-436905ee941a
DTSTART:20191203T080000Z
DTEND:20191204T170000Z
DESCRIPTION:\nThis course covers performance engineering approaches on the 
 compute node level. Even application developers who are fluent in OpenMP a
 nd MPI often lack a good grasp of how much performance could at best be ac
 hieved by their code.\n\nThis is because parallelism takes us only half th
 e way to good performance.\n\nEven worse\, slow serial code tends to scale
  very well\, hiding the fact that resources are wasted. This course convey
 s the required knowledge to develop a thorough understanding of the intera
 ctions between software and hardware. This process must start at the core\
 , socket\, and node level\, where the code gets executed that does the act
 ual computational work. We introduce the basic architectural features and 
 bottlenecks of modern processors and compute nodes.\n\nPipelining\, SIMD\,
  superscalarity\, caches\, memory interfaces\, ccNUMA\, etc.\, are covered
 . A cornerstone of node-level performance analysis is the Roofline model\,
  which is introduced in due detail and applied to various examples from co
 mputational science. We also show how simple software tools can be used to
  acquire knowledge about the system\, run code in a reproducible way\, and
  validate hypotheses about resource consumption. Finally\, once the archit
 ectural requirements of a code are understood and correlated with performa
 nce measurements\, the potential benefit of code changes can often be pred
 icted\, replacing hope-for-the-best optimizations by a scientific process.
 \n\n \n\nThe course is a PRACE training event.\n\n\n	Introduction\n	\n		O
 ur approach to performance engineering\n		Basic architecture of multicore 
 systems: threads\, cores\, caches\, sockets\, memory\n		The important role
  of system topology\n	\n	\n	Tools: topology &amp\; affinity in multicore e
 nvironments\n	\n		Overview\n		likwid-topology and likwid-pin\n	\n	\n	Micro
 benchmarking for architectural exploration\n	\n		Properties of data paths 
 in the memory hierarchy\n		Bottlenecks\n		OpenMP barrier overhead\n	\n	\n	
 Roofline model: basics\n	\n		Model assumptions and construction\n		Simple 
 examples\n		Limitations of the Roofline model\n	\n	\n	Pattern-based perfor
 mance engineering\n	Optimal use of parallel resources\n	\n		Single Instruc
 tion Multiple Data (SIMD)\n		Cache-coherent Non-Uniform Memory Architectur
 e (ccNUMA)\n		Simultaneous Multi-Threading (SMT)\n	\n	\n	Tools: hardware p
 erformance counters\n	\n		Why hardware performance counters?\n		likwid-per
 fctr\n		Validating performance models\n	\n	\n	Roofline case studies\n	\n		
 Dense matrix-vector multiplication\n		Sparse matrix-vector multiplication\
 n		Jacobi (stencil) smoother\n	\n	\n	Optional: The ECM performance model\n
 \n\nhttps://events.prace-ri.eu/event/901/
SUMMARY:Node-Level Performance Engineering @ LRZ
URL;VALUE=URI:https://events.prace-ri.eu/event/901/
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