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DESCRIPTION:\nThis online course covers performance engineering approaches 
 on the compute node level. Even application developers who are fluent in O
 penMP and MPI often lack a good grasp of how much performance could at bes
 t be achieved by their code.\n\nThis is because parallelism takes us only 
 half the way to good performance.\n\nEven worse\, slow serial code tends t
 o scale very well\, hiding the fact that resources are wasted. This course
  conveys the required knowledge to develop a thorough understanding of the
  interactions between software and hardware. This process must start at th
 e core\, socket\, and node level\, where the code gets executed that does 
 the actual computational work. We introduce the basic architectural featur
 es and bottlenecks of modern processors and compute nodes.\n\nPipelining\,
  SIMD\, superscalarity\, caches\, memory interfaces\, ccNUMA\, etc.\, are 
 covered. A cornerstone of node-level performance analysis is the Roofline 
 model\, which is introduced in due detail and applied to various examples 
 from computational science. We also show how simple software tools can be 
 used to acquire knowledge about the system\, run code in a reproducible wa
 y\, and validate hypotheses about resource consumption. Finally\, once the
  architectural requirements of a code are understood and correlated with p
 erformance measurements\, the potential benefit of code changes can often 
 be predicted\, replacing hope-for-the-best optimizations by a scientific p
 rocess.\n\n \n\nThe course is a PRACE training event.\n\n\n	Introduction\
 n	\n		Our approach to performance engineering\n		Basic architecture of mul
 ticore systems: threads\, cores\, caches\, sockets\, memory\n		The importa
 nt role of system topology\n	\n	\n	Tools: topology &amp\; affinity in mult
 icore environments\n	\n		Overview\n		likwid-topology and likwid-pin\n	\n	\
 n	Microbenchmarking for architectural exploration\n	\n		Properties of data
  paths in the memory hierarchy\n		Bottlenecks\n		OpenMP barrier overhead\n
 	\n	\n	Roofline model: basics\n	\n		Model assumptions and construction\n		
 Simple examples\n		Limitations of the Roofline model\n	\n	\n	Pattern-based
  performance engineering\n	Optimal use of parallel resources\n	\n		Single 
 Instruction Multiple Data (SIMD)\n		Cache-coherent Non-Uniform Memory Arch
 itecture (ccNUMA)\n		Simultaneous Multi-Threading (SMT)\n	\n	\n	Tools: har
 dware performance counters\n	\n		Why hardware performance counters?\n		lik
 wid-perfctr\n		Validating performance models\n	\n	\n	Roofline case studies
 \n	\n		Dense matrix-vector multiplication\n		Sparse matrix-vector multipli
 cation\n		Jacobi (stencil) smoother\n	\n	\n	Optional: The ECM performance 
 model\n\n\nhttps://events.prace-ri.eu/event/1052/
SUMMARY:[ONLINE] Node-Level Performance Engineering @ LRZ
URL;VALUE=URI:https://events.prace-ri.eu/event/1052/
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