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BEGIN:VEVENT
DTSTAMP:20260708T214350Z
UID:7b0396f6-ae2a-4769-b32e-e9bb047b6059
DTSTART:20200211T080000Z
DTEND:20200213T153000Z
DESCRIPTION:Important: For the hands-on sessions participants need to bring
  their own laptops with an ssh-client installed.\n\nWith the increasing pr
 evalence of multicore processors\, shared-memory programming models are es
 sential. OpenMP is a popular\, portable\, widely supported\, and easy-to-u
 se shared-memory model. \n\nSince its advent in 1997\, the OpenMP programm
 ing model has proved to be a key driver behind parallel programming for sh
 ared-memory architectures.  Its powerful and flexible programming model h
 as allowed researchers from various domains to enable parallelism in their
  applications.  Over the more than two decades of its existence\, OpenMP 
 has tracked the evolution of hardware and the complexities of software to 
 ensure that it stays as relevant to today’s high performance computing c
 ommunity as it was in 1997.\n\nThis workshop will cover a wide range of  
 topics\, reaching from the basics of OpenMP programming using the "OpenMP 
 Common Core" to really advanced topics. During each day lectures will be m
 ixed with hands-on sessions on the LRZ system IvyMUC.\n\nPreliminary Agend
 a\n\n\n	\n		\n			\n			 \n			\n			\n			Day 1 \n			\n			\n			Day 2 \n			\n	
 		\n			Day 3\n			\n		\n		\n			\n			09:00-10:30\n			\n			\n			Introduction 
 to the OpenMP common core\n			\n			\n			Tasking\n			\n			\n			Tools for Pe
 rformance and Correctness\n			\n		\n		\n			\n			10:30-10:45\n			\n			\n			
 Coffee Break\n			\n			\n			Coffee Break\n			\n			\n			Coffee Break\n			\n	
 	\n		\n			\n			10:45-12:00\n			\n			\n			Decomposing code into patterns fo
 r parallelization\n			\n			\n			Tasking\n			\n			\n			Offloading to Accele
 rators\n			\n		\n		\n			\n			12:00-13:00\n			\n			\n			Lunch Break\n			\n	
 		\n			Lunch Break\n			\n			\n			Lunch Break\n			\n		\n		\n			\n			13:00-1
 4:45\n			\n			\n			Beyond OpenMP common core with tasking and offloading\n
 			\n			\n			Host Performance: NUMA\n			\n			\n			Other Advanced Features 
 of OpenMP 5.0\n			\n		\n		\n			\n			14:45-15:00\n			\n			\n			Coffee Break
 \n			\n			\n			Coffee Break\n			\n			\n			Coffee Break\n			\n		\n		\n			\n
 			15:00-17:00\n			\n			\n			Hands-on time with Parallelware Trainer\n			
 \n			\n			Host Performance: SIMD\n			\n			\n			Roadmap / Outlook\n			(unti
 l 16:30)\n			\n		\n		\n			\n			 \n			\n			\n			17:00-18:00 Guided SuperMU
 C-NG Tour\n			\n			\n			19:00 Social Event (tbc.)\n			\n			\n			 \n			\n	
 	\n	\n\n\nDay 1\n\nThe first day will cover basic parallel programming wit
 h OpenMP using the Parallelware Trainer Software by Appentra Solutions (ht
 tps://www.appentra.com/products/parallelware-trainer/). \n\nWe will presen
 t a unique\, productivity-oriented approach by introducing its usage based
  on common motifs in scientific code\, and how each one will be paralleliz
 ed. This will enable attendees to focus on the parallelization of componen
 ts and how components combine in real applications.\n\nAttendees will use 
 active learning through a carefully selected set of exercises\, building k
 nowledge on parallelization of key motifs (e.g. matrix multiplication\, ma
 p reduce) that are valid across multiple scientific codes in everything fr
 om CFD to Molecular Simulation. \n\nAppentra’s Parallelware tools are ba
 sed on over 10 years of research by co-founder and CEO\, Dr. Manuel Arenaz
 \, who will be the lecturer of the first day. Parallelware  enables the i
 dentification of opportunities for parallelization and the provision of ap
 propriate parallelization methods using state-of-the-art industrial standa
 rds. Parallelware Trainer was developed specifically to help improve the e
 xperience of HPC training\, providing an interactive learning environment 
 that uses examples that are the same or similar to real codes. Parallelwar
 e Trainer provides support for OpenMP (including multi-threading\, offload
 ing and tasking) and OpenACC (for offloading)\, providing users with the o
 pportunity to use GPU services with either OpenMP or OpenACC.\n\nTopics co
 vered on Day 1 include:\n\n\n	The OpenMP Common Core\n	Beyond the OpenMP C
 ommon Core\n	Parallelization with multi-threading\, offloading and tasking
  paradigms\n	Using Parallelware Trainer: A walk-through with PI example\n	
 Practicals: Examples codes PI\, MANDELBROT\, HEAT and LULESHmk\n	Worksheet
 : Parallelizing PI and LULESHmk with OpenMP\n	 Decomposing code into patt
 erns for parallelization\n\n\nDay 2 and 3\n\nDay 2 and 3 will cover advanc
 ed topics like:\n\n\n	Mastering Tasking with OpenMP\, Taskloops\, Dependen
 cies and Cancellation\n	Host Performance: SIMD / Vectorization\n	Host Perf
 ormance: NUMA Aware Programming\, Memory Access\, Task Affinity\, Memory M
 anagement\n	Tool Support for Performance and Correctness\, VI-HPS Tools \n
 	Offloading to Accelerators\n	Other Advanced Features of OpenMP 5.0\n	Futu
 re Roadmap of OpenMP\n\n\nDevelopers usually find OpenMP easy to learn. Ho
 wever\, they are often disappointed with the performance and scalability o
 f the resulting code. This disappointment stems not from shortcomings of O
 penMP but rather with the lack of depth with which it is employed. The lec
 tures on Day 2 and Day 3 will address this critical need by exploring the 
 implications of possible OpenMP parallelization strategies\, both in terms
  of correctness and performance. \n\nWe cover tasking with OpenMP and host
  performance\, putting a focus on performance aspects\, such as data and t
 hread locality on NUMA architectures\, false sharing\, and exploitation of
  vector units. Also tools for performance and correctness will be presente
 d.\n\nCurrent trends in hardware bring co-processors such as GPUs into the
  fold. A modern platform is often a heterogeneous system with CPU cores\, 
 GPU cores\, and other specialized accelerators. OpenMP has responded by ad
 ding directives that map code and data onto a device\, the target directiv
 es. We will also explore these directives as they apply to programming GP
 Us.\n\nOpenMP 5.0 features will be highlighted and the future roadmap of O
 penMP will be presented.\n\nAll topics are accompanied with extensive case
  studies and we discuss the corresponding language features in-depth.\n\nT
 opics might be still subject to change.\n\nFor the hands-on sessions parti
 cipants need to bring their own laptops with an ssh-client installed.\n\nT
 he course is organized as a PRACE training event by LRZ in collaboration w
 ith Appentra Solutions\, Intel and RWTH Aachen.\n\nLecturers\n\nDr. Manuel
  Arenaz is CEO at Appentra Solutions and professor of computer science at 
 the University of A Coruña (Spain). Holds a PhD on advanced compiler tech
 niques for automatic parallelization of scientific codes. After 10+ years 
 teaching parallel programming at undergraduate and PhD levels\, he strongl
 y believes that the next generation of STEM engineers needs to be educated
  in HPC technologies to address the digital revolution challenge. Recently
 \, he co-founded Appentra Solutions to commercialize products and services
  that take advantage of Parallware\, a new technology for semantic analysi
 s of scientific HPC codes.\n\nDr.  Michael Klemm holds an M.Sc.  and a D
 octor of Engineering degree from the Friedrich-Alexander-University Erlang
 en-Nuremberg\, Germany.  Michael Klemm is a Principal Engineer in the Com
 pute Ecosystem Engineering organization of the Intel Architecture\, Graphi
 cs\, and Software group at Intel in Germany.  His areas of interest inclu
 de compiler construction\, design of programming languages\, parallel prog
 ramming\, and performance analysis and tuning.  Michael Klemm joined the 
 OpenMP organization in 2009 and was appointed CEO of the OpenMP ARB in 201
 6.\n\nDr. Christian Terboven is a senior scientist and leads the HPC group
  at RWTH Aachen University. His research interests center around Parallel 
 Programming and related Software Engineering aspects. Dr. Terboven has bee
 n involved in the Analysis\, Tuning and Parallelization of several large-s
 cale simulation codes for various architectures. He is responsible for sev
 eral research projects in the area of programming models and approaches to
  improve the productivity and efficiency of modern HPC systems. He is furt
 her co-author of the new book “Using OpenMP – The Next Step“\, https
 ://www.openmp.org/tech/using-openmp-next-step/ \nhttps://events.prace-ri.e
 u/event/947/
SUMMARY:OpenMP Programming Workshop @ LRZ
URL;VALUE=URI:https://events.prace-ri.eu/event/947/
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